Conventionally, in a data signal line driving circuit and a scanning signal line driving circuit of an image display device, shift registers have been widely used so as to provide synchronized timing that is applied upon sampling inputted video image data, or so as to form a scanning signal to be applied to the scanning signal lines.
In the data signal line driving circuit, a sampling signal is generated so as to write video image data derived from a video image signal in pixels through a data signal line. In this case, when a sampling signal has an overlapped portion with a sampling signal from the preceding stage or the succeeding stage, the resulting video image data fluctuates greatly, causing erroneous image data to be outputted to the data signal line. In order to solve the above-mentioned problems, a conventional shift register 101 has a circuit construction, for example, as shown in FIG. 32.
The shift register 101, shown in FIG. 32, consists of n stages, and each stage is provided with a D-type flip-flop 102, a NAND circuit 103, inverters 104a and 104b and a NOR circuit 105. To the shift register 101, two clock signals SCK and SCKB which have phases different from each other, and a start pulse SSP are inputted.
Each of the clock signals SCK and SCKB is prepared so as to have half the sampling cycle of the inputted video image signal, and in synchronism with the clock signals SCK and SCKB, pulses are successively outputted from the shift registers 101 on the respective stages. With respect to the i-numbered stage (1≦i≦n), an output Qi−1 of the D-type flip-flop 102 on the (i−1)-numbered stage and an output Qi of the D-type flip-flop 102 on the i-numbered stage are inputted to the NAND circuit 103 on the i-numbered stage so that an output signal NSouti is obtained.
Moreover, in order to prevent a sampling signal Si on the i-numbered stage and a sampling signal Si+1 on the (i+1)-numbered stage from overlapping each other, the output signal NSOUTi is not only directly inputted to one of the input terminals of the NOR circuit on the i-numbered NOR circuit 105, but also inputted to a delay circuit constituted by inverters 104a and 104b on two steps. Since the output of the delay circuit is inputted to the other input terminal of the NOR circuit 105, it is possible to shorten the width of the sampling signal Si outputted from the NOR circuit 105 on the i-numbered stage.
The same process as described above is carried out on each of the shift registers 101 on the respective stages so that as illustrated in FIG. 33, sampling signals. S1 to Sn having no overlapped portions with each other are obtained.
Next, referring to FIGS. 34 and 35, an explanation will be given of a conventional shift register 111 installed in a scanning signal line driving circuit.
The scanning signal line driving circuit outputs a scanning signal to each of the scanning signal lines so that video image data is successively written in pixels arranged on a display section. At this time, the pulse output has to be stopped so that the (i+1)-numbered scanning signal is not overlapped with the i-numbered scanning signal or so that a process for refreshing the video image data that has been written on the i-numbered data signal line is carried out.
Therefore, as illustrated in FIG. 34, the conventional shift register 111, installed in the scanning signal line driving circuit, consists of n stages, and each stage is provided with a D-type flip-flop 112, a NAND circuit 113 and a NOR circuit 114. Moreover, to the shift register 111, two clock signals GCK•GCKB, which have phases different from each other, a start pulse GSP and a pulse width control signal PWC are inputted.
In the shift register 111, pulses are successively outputted from the respective stages in synchronism with the clock signals GCK•GCKB. With respect to the i-numbered stage (1≦i≦n), an output Qi−1 of the D-type flip-flop 112 on the (i−1)-numbered stage and an output Qi of the D-type flip-flop 112 on the i-numbered stage are inputted to the NAND circuit 113 on the i-numbered stage so that an output signal NOUTi is obtained. The output signals NOUT1 to NOUTn, thus obtained, are outputted in the same cycles as the respective scanning signals GL1 to GLn.
In the shift register 111, the pulse width control signal PWC is further inputted to one of the input terminals of the NOR circuit 114 on each stage. Moreover, to the other input terminal of the NOR circuit 114 on the i-numbered stage is inputted the output signal NOUTi of the NAND circuit 113 on the i-numbered stage. Consequently, a scanning signal GLi is outputted from the NOR circuit 114 from the i-numbered stage.
The same process as described above is carried out on each of the shift registers 111 on the respective stages so that as illustrated in FIG. 35, sampling signals GL1 to GLn having no overlapped portions with each other are obtained. Therefore, the (i+1)-numbered scanning signal GLi+1 is not overlapped with the i-numbered scanning signal GLi so that a process for carrying out a refreshing process, etc. on video image data that has been written on the i-numbered data signal is provided.
Here, as illustrated in FIG. 36, in the above-mentioned D-type flip-flops 102•112, when a signal A is inputted through the D terminal and two clock signals CK and CKB are inputted through the other terminal, a signal B is outputted from the Q terminal.
However, the conventional shift registers 101•111 require circuits as shown in FIGS. 32 and 34, resulting in a problem of a bulky driving circuit.
In recent years, there have been ever-increasing demands for image display devices having a wider display screen and a narrower frame width with high precision; therefore, it is necessary to make the area of the driving circuit smaller. Moreover, in applications other than image display devices, there are high demands for simplified circuit construction of shift registers. Moreover, with respect to a conventional shift register used for a data signal line driving circuit, an arrangement as shown in FIG. 37 is proposed. In the shift register shown in FIG. 37, an S clock signal SCK is applied with a cycle half the sampling cycle of the inputted video image signal, and an output of the shift register section P1S is successively outputted in synchronism with the clock signal.
With respect to an n-numbered stage of the shift register P1S, an output Qn on the n-numbered stage (SSRn) and an output Qn−1 on the (n−1)-numbered stage (SSRn−1) are used in a NAND_Sn so as to obtain NSOUTn.
A sampling signal on the n-numbered stage is allowed to have a narrower sampling signal by using a NOR_San which takes NOR between the NSOUTn and the sampling pulse width control signal SPWC for controlling the sampling pulse width, so as not to overlap the sampling signal on the (n−1) stage. The same process is carried out on each of the outputs of the shift registers PlS so that, as illustrated in a timing chart in FIG. 38, a sampling signal having no overlapped portion is obtained. In this case, the pulse width control signal SPWC has a frequency twice the frequency of the S clock signal SCK.
Moreover, with respect to a conventional shift register used for a scanning signal line driving circuit, an arrangement as shown in FIG. 39 is proposed. In the shift register shown in FIG. 39, a scanning signal, writes a video image signal applied to a data signal line on pixels arranged on a display section, is successively outputted. In this case, with respect to the n-numbered scanning signal, its output has to be stopped so that it is not overlapped with the (n−1)-numbered scanning signal or so that a process for refreshing the video image data that has been written on the (n−1)-numbered data signal line is carried out.
More specifically, referring to a circuit diagram of FIG. 39 and its timing chart of FIG. 40, an explanation will be given of the operation. In FIG. 39, the output of the shift register P1G is successively released in synchronism with a G clock signal GCK. With respect to an n-numbered stage of the shift register P1G, an output (Qn) on the n-numbered stage (GSRn) and an output (Qn−1) on the (n−1)-numbered stage (GSRn−1) are used in a NAND_Gn so as to obtain NOUTn. The NOUTn are respectively outputted with the same cycle as the scanning signal.
As described earlier, with respect to the n-numbered scanning signal, its output has to be stopped so that it is not overlapped with the (n−1)-numbered scanning signal or so that a process for refreshing the video image data that has been written on the (n−1)-numbered data signal line is carried out or so that a precharging process, etc. is carried out. For this reason, a scanning pulse width control signal GPWC is inputted, and this and NOUTn are used in a NOR_Gn so as to obtain GLn. The GLn forms a scanning signal for driving the n-numbered scanning signal line. At this time, the pulse width control signal GPWC has a frequency twice the frequency of the G clock signal GCK.
Here, in the flip-flop circuit (D-flip-flop) constituting the shift register of FIG. 37 and FIG. 39, as illustrated in FIG. 36, the circuit construction is designed so that, when a signal A is inputted to the D-terminal with two clock signals CK and CKB being inputted through the other terminals, a signal B is outputted.
In general, the power consumption increases in proportion to the frequency, the load capacitance and the square of the voltage. Therefore, for example, in circuits that are connected to an image display device, such as those for generating video image signals for the image display device, or in image display devices, there is a tendency to reduce the driving voltage as small as possible.
For example, in a circuit using monocrystal silicon transistors such as the above-mentioned generation circuit for video image signals, the driving voltage is set to, for example, 5 V or 3.3 V, or a value not more than this value, in most cases.
In contrast, in a circuit using polycrystal silicon thin-film transistors so as to ensure a wider display area, such as pixels, a data signal line driving circuit or a scanning signal line driving circuit, since a difference of threshold voltages between substrates tends to reach as high as several volts (for example, 15 V), the reduction of the driving voltage has not been sufficiently achieved. Therefore, in the case when an input signal lower than the driving voltage of a shift register is inputted to a shift register, a level shifter for voltage-raising the input signal is installed in the shift register. In general, with respect to the input signal for the level shifter, two kinds of signals having two phases are used, and the two kinds of signals have respectively reversed phases.
More specifically, as shown in FIGS. 37 and 39, for example, when an input signal having an amplitude of approximately 5V is inputted to each of shift registers PlS and P1G, two level shifters Ls of the three in the Figure voltage-raises clock signals SCK and GCK to reach the driving voltage (15 V) of the shift registers P1S and P1G. The outputs of these level shifters Ls are inputted to flip-flops SSR1 to SSRx and GSR1 to GSRx that constitute the shift registers P1S and P1G. In synchronism with the outputs of the level shifters Ls thus applied, the shift registers P1S and P1G are allowed to have respective outputs.
However, in various circuits using conventional shift registers as shown in FIGS. 37 and 39, that is, for example, in a data signal line driving circuit, logical circuits (NOR, etc.) are required so as to prevent the sampling signals from overlapped each other, resulting in a large driving circuit; and for example, in a scanning signal line driving circuit, logical circuits (NOR, etc.) are also required so as to prevent the scanning signals from overlapping each other, resulting in a large driving circuit.
Moreover, each of the above-mentioned pulse width control signals SPWC and GPWC has a frequency that is twice the frequency of each of an S clock signal SCK and a G clock signal GCK, resulting in a greater driving frequency.
Moreover, in the shift registers P1S and P1G, after the clock signals SCK, SCKB (with a phase reversed to SCK) and GCK, GCKB (with a phase reversed to GCK) have been shifted in their levels, they are supplied to respective flip-flops constituting the shift register; therefore, the resulting problem is that the greater the distance between the flip-flops SSR1 to SSRx and the distance between the GSR1 to GSR2, the greater the transmission distance, causing an increase in the power consumption. In other words, as the transmission distance becomes longer, the capacitance of the transmission-use signal lines becomes greater, with the result that the level shifters LS require a greater driving capability, thereby resulting in an increase in the power consumption.
Moreover, as in the case when the driving circuit containing level shifters LS is constructed by using polycrystal silicon thin-film transistors, when the level shifter LS has only an insufficient capability, a buffer BUF having a great driving capability needs to be installed immediately after the level shifter LS so as to transmit signal waveforms that are free from rounding; this further causes an increase in the power consumption.
In recent years, there have been ever-increasing demands for image display devices with high precision having a wider display screen and narrower portions other than the display area; therefore, the frequency of clock signals has to be increased, and in response to this, it is required that the number of the stages of the shift registers P1S and P1G be increased and that the area of the driving circuit be minimized.